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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 general description the MAX17117 includes a high-performance step-up regulator, a 350ma low-dropout (ldo) linear regulator, a high-speed operational amplifier, and a high-voltage level-shifting scan driver with gate-shading control. the device is optimized for thin-film transistor (tft) liquid- crystal display (lcd) applications. the step-up dc-dc converter provides the regulated supply voltage for panel source-driver ics. the high 1.2mhz switching frequency allows the use of ultra-small inductors and ceramic capacitors. the current-mode control architecture provides a fast-transient response to pulsed loads typical of source driver loads. the step-up regulator features an adjustable soft-start and an adjust - able cycle-by-cycle current limit. the high-current operational amplifier is designed to drive the lcd backplane (vcom). the amplifier features high output current ( q 200ma typ), fast slew rate (40v/ f s typ), wide bandwidth (16mhz typ), and rail-to-rail inputs and outputs. the low-voltage ldo linear regulator has an integrated 0.8 i pass element and can provide at least 350ma. the output voltage is accurate within q 1%. the high-voltage, level-shifting scan driver with gate- shading control is designed to drive the tft panel gate drivers. its seven outputs swing 40v (maximum) between +35v (maximum) and -15v (minimum) and can swiftly drive capacitive loads. the MAX17117 is available in a 32-pin, 5mm x 5mm, thin qfn package with a maximum thickness of 0.8mm for thin lcd panels. applications notebook computer displays features s 2.3v to 5.5v in supply-voltage range s 1.2mhz current-mode step-up regulator fast-transient response high-accuracy reference (1%) integrated 16v, 2a, 200m i mosfet high efficiency (> 85%) adjustable cycle-by-cycle current limit s high-performance operational amplifier 200ma output short-circuit current 40v/s slew rate 16mhz, -3db bandwidth low-dropout linear regulator high-accuracy output voltage (1.0%) s high-voltage drivers with scan logic +35v to -15v outputs 40v maximum voltage swing gate-shading control s thermal-overload protection s 32-pin, 5mm x 5mm, thin qfn package 19-5241; rev 0; 4/10 simplified operating circuit ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. evaluation kit available system panel v vgl v vgl v main v ghon to vcom backplane scan driver and gate-shading control logic v in v logic ena ldoadj ldoo dts ghon v ghon st ck1 ck3 ck5 ck2 ck4 ck6 vgl in s6 s4 s2 s5 s3 s1 linear regulator setup controller gate- shading timing control MAX17117 lx pgnd fb comp ss agnd (ep) opas out pos op sth ckh1 ckh3 ckh5 ro ckh2 ckh4 ckh6 re vglc part temp range pin-package MAX17117etj+ -40 n c to +85 n c 32 tqfn-ep*
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, ena, fb, comp, ss, dts, ldoadj, st, ck1Cck6, ldoo to agnd ............................... -0.3v to +7.5v pgnd to agnd .................................................... -0.3v to +0.3v lx, opas to pgnd ............................................... -0.3v to +18v ghon to pgnd .................................................... -0.3v to +45v vgl to pgnd ....................................................... -20v to +0.3v ghon to vgl .................................................................... +45v sth, ckh1Cckh6, vglc, ro, re to vgl ......................................... -0.3v to (v ghon + 0.3v) out, pos to pgnd .............................. -0.3v to (v opas + 0.3v) ghon and vgl rms current rating .................................. 0.8a vglc, sth, and ckh1Cckh6 rms current rating ........... 0.8a lx, pgnd rms current rating ............................................ 1.6a continuous power dissipation (t a = +70 n c) 32-pin tqfn (derate 24.9mw/ n c above +70 n c) ....... 1990mw operating temperature range .......................... -40 n c to +85 n c junction temperature ..................................................... +150 n c storage temperature range ............................ -65 n c to +160 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics (v in = +3v, circuit of figure 1, v opas = +8.5v, v ghon = +24v, v vgl = -6.2v, v st = v ck _ = 0v, t a = 0 n c to +85 n c , unless otherwise noted. typical values are at t a = +25 n c.) absolute maximum ratings parameter conditions min typ max units in input voltage range 2.3 5.5 v in undervoltage-lockout threshold v in rising, typical hysteresis = 150mv 1.80 2.00 2.20 v in quiescent current v fb = 1.3v, lx not switching 1.0 2.5 ma v fb = 1.2v, lx switching 2.5 5 in standby current v ena = v vgl = 0v, v in = 5.5v, v ghon = 4v 0.7 2 ma ghon standby current v ena = v vgl = 0v, v in = 5.5v, v ghon = 4v 100 200 f a opas standby current v ena = v vgl = 0v, v in = 5.5v, v ghon = 4v 20 50 f a thermal shutdown temperature rising 145 170 n c step-up regulator output voltage range v in 15 v opas overvoltage threshold opas rising 16.5 17 18 v operating frequency 1000 1200 1400 khz oscillator maximum duty cycle 91 94 97 % fb regulation voltage no load 1.227 1.240 1.252 v fb fault-trip level falling edge 1.05 1.10 1.15 v fault-trigger delay 160 ms fb load regulation 0 < i load < full load -0.2 % fb line regulation v in = 2.5v to 5.5v, t a = +25 n c 0.1 0.25 %/v fb input-bias current v fb = 1.24v, t a = +25 n c 65 200 na fb transconductance d i comp = q 2.5 f a, fb = comp 75 160 280 f s lx current limit r ena = 10k w , duty cycle = 60% 1.6 2 2.4 a lx on-resistance i lx = 1a 200 500 m i lx input-bias current v lx = 13.5v, t a = +25 n c 10 20 f a current-sense transresistance 0.10 0.20 0.30 v/a soft-start pullup current 2 4 6 f a
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = +3v, circuit of figure 1, v opas = +8.5v, v ghon = +24v, v vgl = -6.2v, v st = v ck _ = 0v, t a = 0 n c to +85 n c , unless otherwise noted. typical values are at t a = +25 n c.) parameter conditions min typ max units vcom buffer opas voltage range 5 15 v opas supply current v pos = v opas /2, no load 0.8 1.2 ma out voltage swing high i out = 5ma v opas - 100 v opas - 50 mv out voltage swing low i out = 5ma 50 100 mv out short-circuit current sourcing, short to v opas /2 - 1v 100 200 ma sinking, short to v opas /2 + 1v 100 200 pos input-bias current v pos = v opas /2, t a = +25 n c -50 +50 na pos input-offset voltage v out = v opas /2 -15 +15 mv gain-bandwidth product 8 mhz -3db bandwidth r load = 10k i , c load = 10pf 16 mhz slew rate 5v pulse applied to pos, out measured from 10% to 90% 10 40 v/ f s high-voltage scan driver ghon voltage range 12 35 v vgl voltage range -15 -3 v ghon-to-vgl voltage range v ghon - v vgl 40 v ghon supply current ck1 through ck6 and st low 350 550 f a vgl supply current ck1 through ck6 and st low -500 -300 f a output impedance low sth, ckh_, vglc, i out = -20ma 80 i output impedance high sth, ckh_, vglc, i out = +20ma 80 i gate-shading switch resistance ckh1, ckh3, ckh5, i re = 10ma 100 i ckh2, ckh4, ckh6, i ro = 10ma 100 ro, re resistance range 100 i propagation delay from st rising edge to sth rising edge c load = 100pf, r load = 0 i 100 200 ns propagation delay from st falling edge to sth falling edge c load = 100pf, r load = 0 i 100 200 ns propagation delay from ck_ rising edge to ckh_ rising edge c load = 100pf, r load = 0 i 100 200 ns propagation delay from ck_ falling edge to ckh_ falling edge c load = 100pf, r load = 0 i 100 200 ns sth, vglc, ckh_ rise time c load = 5nf, r load = 0 i ; v ghon = 30v, v vgl = -10v; measured from 10% to 90% 0.5 1 f s sth, vglc, ckh_ fall time c load = 5nf, r load = 0 i ; v ghon = 30v, v vgl = -10v; measured from 10% to 90% 0.5 1 f s sth, ckh_ operating frequency range c load = 5nf, r load = 0 i 100 khz
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 4 ______________________________________________________________________________________ electrical characteristics (continued) (v in = +3v, circuit of figure 1, v opas = +8.5v, v ghon = +24v, v vgl = -6.2v, v st = v ck _ = 0v, t a = 0 n c to +85 n c , unless otherwise noted. typical values are at t a = +25 n c.) electrical characteristics (v in = +3v, circuit of figure 1, v opas = +8.5v, v ghon = +24v, v vgl = -6.2v, v st = v ck_ = 0v, t a = -40 n c to +85 n c , unless oth - erwise noted.) parameter conditions min typ max units gate-shading timing control gate-shading detection threshold dts falling 100 150 mv gate-shading detection current v dts = 0.5v 5 10 15 a dts switch resistance v dts = 1.3v, i dts = 1ma 10 50 i dts rising edge threshold 1.215 1.240 1.265 v dts falling edge threshold 100 150 mv ldo ldoo output voltage range 1.8 v in v dropout voltage v in = 3.3v, v ldoadj = 1.1v, i ldoo = 350ma 300 500 mv ldoo line regulation v in = 2.8v to 5.5v, v ldoo = 2.5v, i ldoo = 100ma 0.1 0.3 %/v ldoo load regulation v ldoo = 2.5v, i ldoo = 1ma to 300ma 0.2 0.5 %/v ldoo current limit v ldoadj = 1.0v 0.4 0.62 0.8 a ldoadj feedback voltage 1.227 1.240 1.252 v ldoadj input-bias current v ldoadj = 1.3v, t a = +25 n c 100 200 na digital inputs st, ck_ input high level 1.8v < v ldoo < 5.5v 0.7 x v ldoo v st, ck_ input low level 1.8v < v ldoo < 5.5v 0.3 x v ldoo v ena input logic-high level 1.8v < v ldoo < 3.0v 0.7 x v ldoo v v ldoo > 3.0v 2.1 v ena input logic-low level 1.8v < v ldoo < 3.0v 0.3 x v ldoo v v ldoo > 3.0v 0.8 v ena resistor range 0 200 k i parameter conditions min typ max units in input voltage range 2.3 5.5 v in undervoltage-lockout threshold v in rising, typical hysteresis = 150mv 1.80 2.20 v in quiescent current v fb = 1.3v, lx not switching 2.5 ma v fb = 1.2v, lx switching 5 in standby current v ena = v vgl = 0v, v in = 5.5v, v ghon = 4v 2 ma ghon standby current v ena = v vgl = 0v, v in = 5.5v, v ghon = 4v 160 f a opas standby current v ena = v vgl = 0v, v in = 5.5v, v ghon = 4v 50 f a thermal shutdown temperature rising 145 n c
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 _______________________________________________________________________________________ 5 electrical characteristics (continued) (v in = +3v, circuit of figure 1, v opas = +8.5v, v ghon = +24v, v vgl = -6.2v, v st = v ck_ = 0v, t a = -40 n c to +85 n c , unless oth - erwise noted.) parameter conditions min typ max units step-up regulator output voltage range v in 15 v opas overvoltage threshold opas rising 16.5 18 v operating frequency 1000 1400 khz oscillator maximum duty cycle 91 97 % fb regulation voltage no load 1.227 1.252 v fb fault-trip level falling edge 1.05 1.15 v fb line regulation v in = 2.5v to 5.5v, t a = +25 n c 0.3 %/v fb input-bias current v fb = 1.3v, t a = +25 n c 200 na fb transconductance d i comp = q 2.5 f a, fb = comp 75 280 f s lx current limit v fb = 1.2v, duty cycle = 60% 1.6 2.4 a lx on-resistance i lx = 1a 500 m i lx input-bias current v lx = 13.5v, t a = +25 n c 20 f a current-sense transresistance 0.10 0.30 v/a soft-start pullup current 2 6 f a vcom buffer opas voltage range 5 15 v opas supply current v pos = v opas /2, no load 1.2 ma out voltage swing high i out = 5ma v opas - 100 mv out voltage swing low i out = 5ma 100 mv out short-circuit current sourcing, short to v opas /2 - 1v 100 ma sinking, short to v opas /2 + 1v 100 pos input-bias current v pos = v opas /2, t a = +25 n c -50 +50 na pos input-offset voltage v out = v opas /2 -15 +15 mv slew rate 5v pulse applied to pos, out measured from 10% to 90% 10 v/ f s high-voltage scan driver ghon voltage range 12 35 v vgl voltage range -15 -3 v ghon-to-vgl voltage range v ghon - v vgl 40 v ghon supply current ck1 through ck6 and st low 550 f a vgl supply current ck1 through ck6 and st low -500 f a output impedance low sth, ckh_, vglc, i out = -20ma 80 i output impedance high sth, ckh_, vglc, i out = +20ma 80 i gate-shading switch resistance ckh1, ckh3, ckh5, i re = 10ma 100 i ckh2, ckh4, ckh6, i ro = 10ma 100 ro, re resistance range 100 i propagation delay from st rising edge to sth rising edge c load = 100pf, r load = 0 i 200 ns
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 6 ______________________________________________________________________________________ electrical characteristics (continued) (v in = +3v, circuit of figure 1, v opas = +8.5v, v ghon = +24v, v vgl = -6.2v, v st = v ck_ = 0v, t a = -40 n c to +85 n c , unless oth - erwise noted.) parameter conditions min typ max units propagation delay from st falling edge to sth falling edge c load = 100pf, r load = 0 i 200 ns propagation delay from ck_ rising edge to ckh_ rising edge c load = 100pf, r load = 0 i 200 ns propagation delay from ck_ falling edge to ckh_ falling edge c load = 100pf, r load = 0 i 200 ns sth, vglc, ckh_ rise time c load = 5nf, r load = 0 i ; v ghon = 30v, v vgl = -10v; measured from 10% to 90% 1 f s sth, vglc, ckh_ fall time c load = 5nf, r load = 0 i ; v ghon = 30v, v vgl = -10v; measured from 10% to 90% 1 f s sth, ckh_ operating frequency range c load = 5nf, r load = 0 i 100 khz gate-shading timing control gate-shutdown detection threshold dts falling 100 150 mv gate-shutdown detection current v dts = 0.5v 5 10 15 a dts switch resistance v dts = 1.3v, i dts = 1ma 50 i dts rising edge threshold 1.210 1.265 v dts falling edge threshold 150 mv ldo ldoo output voltage range 1.8 v in v dropout voltage v in = 3.3v, v ldoadj = 1.1v, i ldoo = 350ma 500 mv ldoo line regulation v in = 2.8v to 5.5v, v ldoo = 2.5v, i ldoo = 100ma 0.3 % /v ldoo load regulation v ldoo = 2.5v, i ldoo = 1ma to 300ma 0.5 % /v ldoo current limit v ldoadj = 1.0v 0.4 0.8 a ldoadj feedback voltage 1.227 1.252 v ldoadj input-bias current v ldoadj = 1.3v, t a = +25 n c 200 na digital inputs st, ck_ input high level 1.8v < v ldoo < 5.5v 0.7 x v ldoo v st, ck_ input low level 1.8v < v ldoo < 5.5v 0.3 x v ldoo v ena input logic-high level 1.8v < v ldoo < 3.0v 0.7 x v ldoo v v ldoo > 3.0v 2.1 ena input logic-low level 1.8v < v ldoo < 3.0v 0.3 x v ldoo v v ldoo > 3.0v 0.8 ena resistor range 0 200 k i
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 _______________________________________________________________________________________ 7 typical operating characteristics (t a = +25c, unless otherwise noted.) step-up regulator efficiency vs. load current MAX17117 toc01 load current (ma) efficiency (%) 100 10 50 60 70 80 90 100 40 1 1000 v in = 5.0v v in = 3.0v v in = 2.3v v main = 8.5v step-up regulator line regulation vs. input voltage MAX17117 toc02 in voltage (v) line regulation (%) 5.1 4.7 4.3 3.9 3.5 3.1 2.7 0.05 0.10 i main = 200ma i main = 0ma 0.15 0.20 0.25 0 2.3 5.5 load current (ma) load-regulation error (%) 100 10 1 1000 step-up regulator output load regulation vs. load current MAX17117 toc03 -0.40 -0.30 -0.20 -0.10 0 0.10 -0.50 v in = 5.0v v in = 2.3v v in = 3.0v step-up converter peak inductor current limit vs. r ena MAX17117 toc04 r ena (ki) peak inductor current limit (a) 200 150 100 50 1.0 1.5 v in = 3.3v v main = 8.5v v ldo = 2.5v l1 = 10h 2.0 2.5 3.0 0.5 0 250 step-up regulator load-transient response (20ma to 300ma) MAX17117 toc05 inductor current 1a/div v main (ac-coupled) 200mv/div i main 200ma/div 20ma l1 = 10h r comp = 56.2ki c comp = 1000pf v lx 10v/div 0v 0v 0a 100s/div step-up regulator pulsed load-transient response (20ma to 1a) MAX17117 toc06 inductor current 500ma/div v main (ac-coupled) 100mv/div i main 1a/div 20ma l1 = 10h r comp = 56.2ki c comp = 1000pf v lx 10v/div 0v 0v 0a 10s/div load current (ma) load-regulation error (%) 100 10 1 1000 ldo output load regulation vs. load current MAX17117 toc07 -0.40 -0.30 -0.20 -0.10 0 0.10 -0.50 v in = 3.0v v in = 5.0v
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 8 ______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25c, unless otherwise noted.) MAX17117 toc08 in voltage (v) line regulation (%) ldo line regulation vs. input voltage 0.03 0.06 0.09 0.12 0.15 0 5.4 5.1 4.8 4.5 4.2 3.9 3.6 3.3 3.0 2.7 i ldo = 250ma i ldo = 100ma power-up sequence (ck1 and st connected to v ldo ) MAX17117 toc09 v vgl 10v/div v sth 50v/div v ckh1 50v/div v vglc 20v/div v in 5v/div v ldo 5v/div v main 10v/div v ghon 20v/div 0v 0v 0v 0v 0v 0v 0v 0v 40ms/div operational amplifier load-transient response MAX17117 toc10 i vcom 100ma/div v vcom (ac-coupled) 1v/div 0mv 0ma 2s/div operational amplifier large-signal step response MAX17117 toc11 v vcom 2v/div v pos 2v/div 0v 0v 200ns/div operational amplifier small-signal step response MAX17117 toc12 v vcom (ac-coupled) 100mv/div v pos (ac-coupled) 100mv/div 0mv 0mv 200ns/div ckh_ output waveforms with logic input and gate-shading control MAX17117 toc13 v ck1 5v/div v ck2 5v/div v dts 2v/div v ckh1 20v/div v ckh2 20v/div 0v 0v 0v 0v 0v 4s/div
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 _______________________________________________________________________________________ 9 pin configuration pin description MAX17117 thin qfn top view 29 30 28 27 12 11 13 ck4 ck2 ck1 st ck6 14 ck5 comp pos out fb ro ghon 1 + 2 in 4 5 6 7 23 24 22 20 19 18 ldoo ldoadj ckh2 ckh3 ckh4 ckh5 ck3 opas 3 21 31 10 dts ckh6 32 9 ss ep vglc ena 26 15 ckh1 lx 25 16 sth re vgl 8 17 pgnd pin name function 1C5, 7 ck5Cck1, ck6 level-shifter logic-level inputs 6 st start-pulse, level-shifter logic-level input 8 re gate-shading discharge for ckh2, ckh4, and ckh6 9 vglc vgl voltage output 10C15 ckh6Cckh1 level-shifter outputs 16 sth start-pulse level-shifter output 17 vgl gate-off supply. vgl is the negative supply voltage for the sth, ckh1Cckh6, and vglc high-volt - age driver outputs. bypass to pgnd with a minimum of 0.1 f f ceramic capacitor. 18 ghon gate-on supply. ghon is the positive supply voltage for the sth, ckh1Cckh6, and vglc high- voltage scan-driver outputs. bypass to pgnd with a minimum of 0.1 f f ceramic capacitor. 19 ro gate-shading discharge for ckh1, ckh3, and ckh5 20 out operational amplifier output 21 pos operational amplifier noninverting input 22 opas operational amplifier supply input. connect to v main (figure 1) and bypass to agnd with a 0.1 f f or greater ceramic capacitor. 23 comp compensation for error amplifier. connect a series rc from this pin to agnd. typical values are 56k i and 1000pf. 24 fb step-up regulator feedback. reference voltage is 1.24v nominal. connect the midpoint of an exter - nal resistor-divider to fb and minimize trace area. set v main according to v main = 1.24v (1 + r1/r2).
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 10 _____________________________________________________________________________________ pin description (continued) pin name function 25 pgnd power ground. source connection of the internal step-up regulator power switch. 26 lx switching node. connect inductor/catch diode here and minimize trace area for lowest emi. 27 ena chip-enable control and ocp set input. when ena = low, the step-up converter and op amp are disabled, the ldo remains active, and the level-shifter outputs are high impedance. 28 in step-up regulator and low-dropout regulator supply. bypass in to agnd with a 1 f f or greater ceramic capacitor. 29 ldoo internal linear regulator output. bypass ldoo to agnd with a 1 f f capacitor. 30 ldoadj linear regulator feedback input. reference voltage is 1.24v nominal. 31 dts gate-shading discharge time adjust 32 ss step-up regulator soft-start control ep exposed backside pad. connect to the analog ground plane for proper electrical and thermal performance.
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 ______________________________________________________________________________________ 11 figure 1. typical application circuit v vgl -6.0v, 10ma v in 2.2f c1 1f c set 100pf v ghon v logic 0.1f 86.6i 0.22f 0.1f 0.1f 0.22f v ghon v main 8.5v, 200ma to vcom backplane 23v, 25ma d3 d1 d4 0.1f d2 c3 10f 10h c4 10f l1 6.2v, 200mw d5 r ena ena pgnd fb comp ss opas pos sth ckh1 ckh3 ckh5 ro ckh2 ckh4 ckh6 out lx ldoadj ldoo dts ghon v vgl 0.1f st panel ck1 ck3 ck5 ck2 ck4 ck6 vgl 62ki agnd (ep) in c2 1f c5 10f c6 10f r comp 56.2ki r 1 102ki r5 r6 49.9ki r set 29.4ki 51.1ki r4 56.2ki r3 56.2ki r2 17.4ki c comp 1000pf c ss 0.33f 0.1f r 0 1ki system re vglc r e 1ki MAX17117
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 12 _____________________________________________________________________________________ typical application circuit the MAX17117 typical application circuit (figure 1) gen - erates a +8.5v source-driver supply and approximately +23v and -6v gate-driver supplies for tft displays. the input voltage range for the ic is from +2.3v to +5.5v, but the circuit in figure 1 is designed to run from 2.5v to 3.6v. table 1 lists the recommended components and table 2 lists the component suppliers. detailed description the MAX17117 includes a high-performance step-up regulator, a 350ma low-dropout (ldo) linear regulator, a high-speed operational amplifier, and a high-voltage, level-shifting scan driver with gate-shading control. figure 2 shows the functional diagram. step-up regulator the step-up regulator employs a peak current-mode control architecture with a fixed 1.2mhz switching fre - quency that maximizes loop bandwidth and provides a fast-transient response to pulsed loads found in source drivers of tft lcd panels. the high switching frequency allows the use of low-profile inductors and ceramic capacitors to minimize the thickness of lcd panel designs. the integrated high-efficiency mosfet reduces the number of external components required. the output voltage can be set from v in to 15v with an external resistive voltage-divider. table 1. component list table 2. component suppliers designation description c1, c2 1 f f 10%, 16v x5r ceramic capacitors (0603) murata grm188r61c105k tdk c1608x5r1c105k c3 10 f f q 10%, 10v x5r ceramic capacitor (0805) tdk c2012x5r1a106k murata grm21br61a106k c4, c5, c6 10 f f q 10%, 16v x5r ceramic capaci - tors (1206) murata grm31cr61c106k tdk c3216x5r1c106k d1 1a, 30v schottky diode (s-flat) central cmmsh1-40 lead free nihon ep10qy03 toshiba crs02 (te85l, q, m) d2, d3, d4 200ma, 100v dual diodes (sot23) fairchild mmbd4148se (top mark: d4) central cmpd7000+ (top mark: c5c) d5 6.2v, 200mw zener diode (sod-323) rohm udzste-176.2b fairchild mm3z6v2b l1 10 f h, 1.85a, 74.4m i inductor (6mm x 6mm x 3mm) sumida cdrh5d28rhpnp-100m supplier website central semiconductor corp. www.centralsemi.com fairchild semiconductor www.fairchildsemi.com murata electronics north america, inc. www.murata-northamerica.com nihon inter electronics corp. www.niec.co.jp rohm co., ltd. www.rohm.com sumida corp. www.sumida.com tdk corp. www.component.tdk.com toshiba america electronic components, inc. www.toshiba.com/taec
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 ______________________________________________________________________________________ 13 figure 2. functional diagram system panel v vgl v vgl v ghon v main to vcom backplane scan driver and gate- shading control logic v in v logic ena ldoadj ldoo dts s dts ghon v ghon st ck1 ck3 ck5 ck2 ck4 ck6 vgl in s6 s4 s2 s5 s3 s1 linear regulator set-up controller gate- shading timing control MAX17117 lx pgnd fb comp ss agnd (ep) opas out pos op sth ckh1 ckh3 ckh5 ro ckh2 ckh4 ckh6 re vglc
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 14 _____________________________________________________________________________________ the regulator controls the output voltage and the power delivered to the output by modulating the duty cycle (d) of the internal power mosfet in each switching cycle. the duty cycle of the mosfet is approximated by: main in main v v d v ? figure 3 shows the step-up regulator block diagram. an error amplifier compares the signal at fb to 1.24v and changes the comp output. the voltage at comp determines the current trip point each time the internal mosfet turns on. as the load varies, the error amplifier sources or sinks current to the comp output accord - ingly to produce the inductor peak current necessary to service the load. to maintain stability at high duty cycles, a slope compensation signal is summed with the current- sense signal. on the rising edge of the internal clock, the controller sets a flip-flop, turning on the n-channel mosfet and apply - ing the input voltage across the inductor. the current through the inductor ramps up linearly, storing energy in its magnetic field. once the sum of the current-feedback signal and the slope compensation exceed the comp voltage, the controller resets the flip-flop and turns off the mosfet. since the inductor current is continuous, a transverse potential develops across the inductor that turns on the diode (d1). the voltage across the inductor then becomes the difference between the output voltage and the input voltage. this discharge condition forces the current through the inductor to ramp back down, transferring the energy stored in the magnetic field to the output capacitor and the load. the mosfet remains off for the rest of the clock cycle. undervoltage lockout (uvlo) the uvlo circuit compares the input voltage at in with the uvlo threshold (2.0v typ) to ensure that the input voltage is high enough for reliable operation. the 150mv (typ) hysteresis prevents supply transients from caus - ing a restart. once the input voltage exceeds the uvlo rising threshold, startup begins. when the input voltage falls below the uvlo falling threshold, the controller turns off the main step-up regulator. figure 3. step-up regulator block diagram fb error amp comp 1.24v pwm comparator current sense 1.2mhz oscillator slope comp ilim comparator logic and driver i limit lx pgnd clock 1.10v to fault logic fault comparator
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 ______________________________________________________________________________________ 15 overvoltage protection the MAX17117 monitors opas for an overvoltage con - dition. if the opas voltage is above 17v (typ), the MAX17117 disables the gate driver of the step-up regula - tor and prevents the internal mosfet from switching. the opas overvoltage condition does not set the fault latch. overcurrent protection the step-up regulator features an adjustable cycle- by-cycle current limit. the inductor current is sensed through the lx switch during the lx switch on-time. if the peak inductor current rises above the current-limit threshold set by r ena , the lx switch immediately turns off until the next switching cycle, effectively limiting the peak-inductor current each cycle. soft-start the soft-start feature effectively limits the inrush current at startup by slowly raising the regulation voltage of the step-up converters feedback pin (v fb ) at a rate deter - mined by the selection of the soft-start capacitor (c ss ). at startup, once ena is pulled high through r ena , an internal 4 f a (typ) current source begins to charge the soft-start capacitor (c ss ), slowly bringing up the volt - age at the soft-start pin (v ss ). v fb follows v ss for v ss < 1.24v. once v ss exceeds 1.24v, v fb remains at 1.24v, allowing v main to reach its full regulation voltage. fault protection during steady-state operation, the MAX17117 monitors the fb voltage. if the fb voltage falls below 1.1v (typ), the MAX17117 activates an internal fault timer. if there is a continuous fault more than 160ms (typ), the MAX17117 sets the fault latch, turning off all outputs except ldoo. once the fault condition is removed, cycle the input volt - age to clear the fault latch and reactivate the device. the fault-detection circuit is disabled during the soft-start time. operational amplifier the MAX17117 has an operational amplifier that is typically used to drive the lcd backplane (vcom) or the gamma-correction-divider string. the operational amplifier features q 200ma (typ) output short-circuit cur - rent, 40v/ f s (typ) slew rate, and 16mhz (typ) bandwidth. while the op amp is a rail-to-rail input and output design, its accuracy is significantly degraded for input voltages within 1v of its supply rails (opas and agnd). short-circuit current limit the operational amplifier limits short-circuit current to approximately q 200ma (typ) if the output is directly shorted to opas or to agnd. if the short-circuit condi - tion persists, the junction temperature of the ic rises until it reaches the thermal-shutdown threshold (+170 n c typ). once the junction temperature reaches the thermal-shut - down threshold, an internal thermal sensor immediately shuts down all outputs until the input voltage is cycled off, then on again. driving pure capacitive loads the operational amplifier is typically used to drive the lcd backplane (vout) or the gamma-correction-divider string. the lcd backplane consists of a distributed series capacitance and resistance, a load that can be easily driven by the operational amplifier. however, if the operational amplifier is used in an application with a pure capacitive load, steps must be taken to ensure stable operation. as the operational amplifiers capacitive load increases, the amplifiers bandwidth decreases and gain peaking increases. a 5 i to 50 i small resistor placed between vout and the capacitive load reduces peak - ing, but also reduces the gain. an alternative method of reducing peaking is to place a series rc network (snubber) in parallel with the capacitive load. the rc network does not continuously load the output or reduce the gain. typical values of the resistor are between 100 i and 200 i and the typical value of the capacitor is 10pf. high-voltage scan driver the high-voltage, level-shifting scan driver with gate- shading control is designed to drive the tft panel gate drivers. its seven outputs swing 40v (maximum) between +35v (maximum) and -15v (minimum) and can swiftly drive capacitive loads. the driver outputs (sth, ckh_) swing between their power-supply rails (ghon and vgl), according to the input logic levels on their corresponding inputs (st, ck_) except during a gate- shading period. during a gate-shading period, a ckh_ output driver becomes high impedance and an internal switch connected between the ckh_ outputs capaci - tive load and either ro or re closes (s1Cs6) whenever the state of its corresponding ck_ input is logic-low. this allows part of an outputs ghon-to-vgl transition to be completed by partially discharging its capacitive load through an external resistor attached to either ro or re for a duration set by the gate-shading period. see figure 4.
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 16 _____________________________________________________________________________________ if the gate-shading control is enabled, a gate-shading period is initiated by a falling edge of a ck_ input when - ever v dts is less than 100mv. once the gate-shading period is initiated, a switch across c set (s dts ) opens, allowing c set to be charged through r set . once v dts reaches 1.24v, s dts closes to discharge c set , the gate-shading period is terminated, and the ckh_ output states are directly determined by their corresponding ck_ input logic states again. once a gate-shading period is initiated, v dts must charge to 1.24v and sub - sequently discharge back below 100mv, before the next ck_ falling can activate a new gate-shading period. by configuring r set and c set as shown in figure 1, the gate-shading period time duration is determined by r set and c set and v ldoo (see the setting the gate-shading period time duration section). the gate-shading control can be disabled by removing r set . if r set is removed, the states of the ckh_ outputs are always determined by their corresponding ck_ input logic states. see figure 5. low-dropout linear regulator (ldo) the MAX17117 has an integrated 0.8 i pass element and can provide at least 350ma. the output voltage is accurate within q 1%. thermal-overload protection when the junction temperature exceeds t j = +170 n c (typ), a thermal sensor activates a fault-protection latch, which shuts down all outputs, allowing the ic to cool down. all outputs remain off until the ic cools and the input voltage is cycled below, then back above the in uvlo threshold. the thermal-overload protection protects the ic in the event of fault conditions. for continuous operation, do not exceed the absolute maximum junction temperature rating of t j = +150 n c. figure 4. scan-driver block diagram ckh1 ckh3 ckh5 s1 s3 s5 ro s dts c set r o r set ldo ldoo ck1 ck2 ck3 ck4 ck5 ck6 level shifter and gate-shading logic dts ckh2 ckh4 ckh6 s2 s4 s6 re r e MAX17117
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 ______________________________________________________________________________________ 17 figure 5. scan-driver operation with gate-shading control enabled ck1 0 0 0 0 0 0 1.24v 0 0 0 0 0 0 0 ck2 ck3 ck4 ck5 ck6 dts ckh1 ckh2 ckh3 ckh4 ckh5 ckh6
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 18 _____________________________________________________________________________________ design procedure main step-up regulator inductor selection the minimum inductance value, peak current rating, and series resistance are factors to consider when select - ing the inductor. these factors influence the converters efficiency, maximum output-load capability, transient- response time, and output-voltage ripple. physical size and cost are also important factors to be considered. the maximum output current, input voltage, output volt - age, and switching frequency determine the inductor value. very high-inductance values minimize the current ripple and therefore reduce the peak current, which decreases core losses in the inductor and i 2 r losses in the entire power path. however, large inductor values also require more energy storage and more turns of wire, which increase physical size and can increase i 2 r loss - es in the inductor. low-inductance values decrease the physical size but increase the current ripple and peak current. finding the best inductor involves choosing the best compromise among circuit efficiency, inductor size, and cost. the equations used here include a constant called lir, which is the ratio of the inductor peak-to-peak ripple cur - rent to the average dc inductor current at the full-load current. the best trade-off between inductor size and circuit efficiency for step-up regulators generally has an lir between 0.3 and 0.5. however, depending on the ac characteristics of the inductor core material and ratio of inductor resistance to other power-path resistances, the best lir can shift up or down. if the inductor resis - tance is relatively high, more ripple can be accepted to reduce the number of turns required and increase the wire diameter. if the inductor resistance is relatively low, increasing inductance to lower the peak current can decrease losses throughout the power path. if extremely thin high-resistance inductors are used, as is common for lcd panel applications, the best lir can increase to between 0.5 and 1.0. once a physical inductor is chosen, higher and lower values of the inductor should be evaluated for efficiency improvements in typical operating regions. in figure 1, the lcds gate-on and gate-off supply voltages are generated from two unregulated charge pumps driven by the step-up regulators lx node. the additional load on lx must therefore be considered in the inductance and current calculations. the effective maximum output current, i main(eff), becomes the sum of the maximum load current of the step-up regulators output plus the contributions from the positive and nega - tive charge pumps: main(eff) main(max) vn vn vp vp i i n i (n 1) i = + + + where i main(max) is the maximum step-up output cur - rent, n vn is the number of negative charge-pump stag - es, n vp is the number of positive charge-pump stages, i vn is the negative charge-pump output current, and i vp is the positive charge-pump output current, assuming the initial pump source for i vp is v main . calculate the approximate inductor value using the typical input voltage (v in ), the maximum output cur - rent (i main(eff) ), the expected efficiency ( e typ ) taken from an appropriate curve in the typical operating characteristics , the desired switching frequency (f osc ), and an estimate of lir based on the above discussion: 2 in main in typ main main(eff) osc v v v l v i f lir ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? choose an available inductor value from an appropriate inductor family. calculate the maximum dc input current at the minimum input voltage v in(min) using conserva - tion of energy and the expected efficiency at that operat - ing point ( e min ) taken from an appropriate curve in the typical operating characteristics : main(eff) main in(dc,max) in(min) min i v i v = calculate the ripple current at that operating point and the peak current required for the inductor: ( ) in(min) main in(min) ripple main osc v v v i l v f ? = ripple peak in(dc,max) i i i 2 = + the inductors saturation current rating and the MAX17117 lx current limit should exceed i peak and the inductors dc current rating should exceed i in(dc,max) . for good efficiency, choose an inductor with less than 0.1 i series resistance. considering the typical application circuit, the maximum load current (i main(max) ) is 200ma, with an 8.5v output and a typical input voltage of 3.3v. the effective full-load step-up current is: main(eff) i 200ma 1 10ma (2 1) 25ma 285ma = + + + =
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 ______________________________________________________________________________________ 19 choosing an lir of 0.2 and estimating efficiency of 85% at this operating point: 2 3.3v 8.5v 3.3v 0.85 l 9.7 h 8.5v 0.285a 1.2mhz 0.2 ? ? ? ? ?? ? = ? ? ? ?? ? ? ? ? ?? ? a 10 f h inductor is chosen. then, using the circuits minimum input voltage (3.0v) and estimating efficiency of 83% at that operating point: in(dc,max) 0.285a 8.5v i 0.973a 3v 0.83 = the ripple current and the peak current at that input volt - age are: ( ) ripple 3v 8.5v 3v i 0.162a 10 h 8.5v 1.2mhz ? = peak 0.162a i 0.973a 1.05a 2 = + = peak inductor current-limit setting connecting r ena between the ena pin and the ldoo output, as shown in figure 1, allows the inductor peak current limit to be adjusted up to 2a max by choosing the appropriate r ena resistor with the following equation: ldoo ena ocp (v 1.25v)(80000) r i ? the above threshold set by r ena varies depending on the step-up converters input voltage, output voltage, and duty cycle. place r ena close to the ic such that the connection between r ena and the ena pin is as short as possible. output capacitor selection the total output-voltage ripple has two components: the capacitive ripple caused by the charging and discharg - ing of the output capacitance, and the ohmic ripple due to the capacitors equivalent series resistance (esr): ripple ripple(c) ripple(esr) v v v = + main main in ripple(c) out main osc i v v v c v f ? ? ? ? ? ? ? and: ripple(esr) peak esr(cout) v i r where i peak is the peak inductor current (see the inductor selection section). for ceramic capacitors, the output-voltage ripple is typically dominated by v ripple(c) . the voltage rating and temperature charac - teristics of the output capacitor must also be considered. input-capacitor selection the input capacitor (c3) reduces the current peaks drawn from the input supply and reduces noise injec - tion into the ic. a 10 f f ceramic capacitor is used in the typical application circuit (figure 1) because of the high source impedance seen in typical lab setups. actual applications usually have much lower source impedance since the step-up regulator often runs directly from the output of another regulated supply. rectifier diode the MAX17117 high switching frequency demands a high-speed rectifier. schottky diodes are recommended for most applications because of their fast recovery time and low forward voltage. in general, a 1a schottky diode complements the internal mosfet well. output-voltage selection the output voltage of the main step-up regulator is adjusted by connecting a resistive voltage-divider from the output (v main ) to agnd with the center tap con - nected to fb (see figure 1). select r2 in the 10k i to 50k i range. calculate r1 with the following equation: main ref v r1 r2 1 v ? ? = ? ? ? ? ? place r1 and r2 close to the ic such that the connec - tions between these components and the fb pin are kept as short as possible. loop compensation choose r comp to set the high-frequency integrator gain for fast-transient response. choose c comp to set the integrator zero to maintain loop stability. for low-esr output capacitors, use the following equa - tions to obtain stable performance and good transient response: in main out comp main(max) 1.45k v v c r l i main main(max) comp 2 in comp 40 v l i c (v ) r to further optimize transient response, vary r comp in 20% steps and c comp in 50% steps while observing transient-response waveforms.
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 20 _____________________________________________________________________________________ operational amplifier output voltage using the buffer configuration as shown in figure 1, the output voltage of the operational amplifier is adjusted by connecting a resistive voltage-divider from the output (v main ) to agnd with the center tap connected to pos (see figure 1). select r3 in the 10k i to 100k i range. calculate r4 with the following equation: main out v r3 r4 1 v ? ? ? ? = ? ? ? ? ? place r3 and r4 close to the ic such that the connec - tions between these components and the pos pin are kept as short as possible. ldo output voltage the output voltage of the ldo is adjusted by connect - ing a resistive voltage-divider from the output (v ldoo ) to agnd with the center tap connected to ldoadj (see figure 1). select r6 in the 10k i to 50k i range. calculate r5 with the following equation: ldoo v r5 r6 1 1.24v ? ? = ? ? ? ? ? place r5 and r6 close to the ic such that the connec - tions between these components and the ldoadj pin are kept as short as possible. connect a 1 f f low esr capacitor between ldoo and agnd to ensure stability and to provide good output- transient performance. scan driver setting the gate-shading period time duration to set the gate-shading period time duration, configure r set and c set as shown in figure 1. choose a c set value greater than 35pf, then calculate the required r set value that gives the desired gate-shading period time duration with the following equation: set set ldoo t r 1.24v ln 1 c v ? = ? ? ? ? ? ? ? increase or decrease c set as needed and repeat the above calculation to achieve the desired gate-shading period time duration, while ensuring c set remains great - er than 35pf and r set is within the 8k i to 100k i range. place r set and c set close to the ic such that the con - nections between these components and the dts pin are kept as short as possible. gate-shading discharge resistors for proper operation, choose r o and r e discharge resistors that are greater than 100 i . place r o and r e close to the ic such that the connections between these components and their respective pins are kept as short as possible. applications information power dissipation an ics maximum power dissipation depends on the thermal resistance from the die to the ambient environ - ment and the ambient temperature. the thermal resis - tance depends on the ic package, pcb copper area, other thermal mass, and airflow. the MAX17117, with its exposed backside paddle sol - dered to 1in 2 of pcb copper, can dissipate approximate - ly 1990mw into +70 n c still air. more pcb copper, cooler ambient air, and more airflow increase the possible dissipation, while less copper or warmer air decreases the ics dissipation capability. the major components of power dissipation are the power dissipated in the step- up regulator and the power dissipated by the operational amplifiers. the MAX17117s largest on-chip power dissipation occurs in the step-up switch, the vcom amplifier, the ckh_ level shifters, and the ldo. step-up regulator the largest portions of the power dissipated by the step-up regulator are the internal mosfet, the induc - tor, and the output diode. if the step-up regulator with 3.3v input and 285ma output has approximately 85% efficiency, approximately 5% of the power is lost in the internal mosfet, approximately 3% in the inductor, and approximately 5% in the output diode. the remaining few percent are distributed among the input and out - put capacitors and the pcb traces. if the input power is approximately 2.85w, the power lost in the internal mosfet is approximately 143mw. operational amplifier the power dissipated in the operational amplifier depends on the output current, the output voltage, and the supply voltage: ( ) source vcom_source avdd vcom pd i v v = ? sink vcom_sink vcom pd i v = where i vcom _ source is the output current sourced by the operational amplifier, and i vcom _ sink is the output current that the operational amplifier sinks. in a typical
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 ______________________________________________________________________________________ 21 case where the supply voltage is 8.5v and the output voltage is 4.25v with an output source current of 30ma, the power dissipated is 128mw. ldo the power dissipated in the ldo depends on the ldos output current, input voltage, and output voltage: ( ) ldo ldoo in ldoo pd i v v = ? scan-driver outputs the power dissipated by the six ckh_ scan-driver out - puts depends on the scan frequency, the capacitive load on each output, and the difference between the ghon and vgl supply voltages: ( ) 2 scan scan panel ghon vgl pd 6 f c v v = ? if the scan frequency is 50khz, the load of the six ckh_ outputs is 3.4nf, and the supply voltage difference is 30v, then the power dissipated is 0.92w. pcb layout and grounding careful pcb layout is important for proper operation. use the following guidelines for good pcb layout: ? minimize the area of high-current loops by placing the inductor, output diode, and output capacitors near the input capacitors and near lx and pgnd. the high- current input loop goes from the positive terminal of the input capacitor to the inductor, to the ics lx pin, out of pgnd, and to the input capacitors negative ter - minal. the high-current output loop is from the positive terminal of the input capacitor to the inductor, to the output diode (d1), to the positive terminal of the output capacitors, reconnecting between the output capaci - tor and input capacitor ground terminals. connect these loop components with short, wide connections. avoid using vias in the high-current paths. if vias are unavoidable, use many vias in parallel to reduce resis - tance and inductance. ? create a power ground island (pgnd) consisting of the input and output capacitor grounds, pgnd pin, and any charge-pump components. connect all these together with short, wide traces or a small ground plane. maximizing the width of the power ground trac - es improves efficiency and reduces output-voltage ripple and noise spikes. create an analog ground plane (agnd) consisting of all the feedback-divider ground connections; the operational-amplifier-divid - er ground connection; the opas bypass capacitor ground connection; the comp, ss, and set capaci - tor ground connections; and the devices exposed backside pad. connect the agnd and pgnd islands by connecting the pgnd pin directly to the exposed backside pad. make no other connections between these separate ground planes. ? place the feedback voltage-divider resistors as close as possible to their respective feedback pins. the dividers center trace should be kept short. placing the resistors far away causes the feedback trace to become an antenna that can pick up switching noise. care should be taken to avoid running the feedback trace near lx or the switching nodes in the charge pumps. ? place the in pin bypass capacitor as close as pos - sible to the device. the ground connections of the in bypass capacitor should be connected directly to agnd at the backside pad of the ic. ? minimize the length and maximize the width of the traces between the output capacitors and the load for best transient responses. ? minimize the size of the lx node while keeping it wide and short. keep the lx node away from the feedback node and analog ground. use dc traces as a shield if necessary. refer to the MAX17117 evaluation kit for an example of proper board layout. chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. 32 tqfn-ep t3255n+1 21-0140
internal-switch boost regulator with integrated 7-channel scan driver, op amp, and ldo MAX17117 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/10 initial release

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